5-Stage Pipeline

Instruction pipelining is a technique that allows faster CPU throughput, that is the number of instructions that can be executed in a unit of time. Each instruction is split up such that instructions can be executed in parallel and can be processed concurrently, rather than processing each instruction sequentially. In an ideal pipeline architecture, the execution of the first instruction requires as many clock cycles as how many stages there are, but the second instruction will be completed only after one additional cycle, as well as every following instruction. One can deduce that the number of clock cycles $T_k$ with this pipeline technology is $T_k=k+(n-1)$ , where $k$ is the number of this pipeline's stages and $n$ is the number of instructions of the program considered. Therefore, $T_k=5+(10-1)=5+9=\boxed{14}$ .