what will be the logic level at f and g for the input pattern A = 1 and B = 1 ?
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A = 1 and B = 1 into the leftmost NAND gate will output a C = 0.
Next, we have inputs A = 1 & C = 0 into the upper middle OR gate for an output D = 1 and inputs B = 1 & C = 0 into the lower middle NAND gate for an output E = 1.
Finally, we have inputs D = 1 & E = 1 into the upper right NAND gate for an output F = 0 and the same inputs D = 1 & E = 1 into the lower right AND gate for an output G = 1.
Answer = FG = 01