Suppose the size of hardware cache is 5*1024 words and the cache is 4-way associative, then what is the maximum size of a cache block in words? Recall that a block is the unit of transfer between the cache and the memory, which means that any cache miss will not only load the word at the desired memory address but also the nearby words all of which constitutes a total of block-size number of words. Also assume that the only mechanisms used to manage the cache are bits extraction and tag matching.
Give -1 as your answer if the question requires more information.
Else -2 if an answer does not exist or is not possible.
Else double your answer if the question contains more "numeric" information then is actually required to answer.
Else submit the answer you got.
This section requires Javascript.
You are seeing this because something didn't load right. We suggest you, (a) try
refreshing the page, (b) enabling javascript if it is disabled on your browser and,
finally, (c)
loading the
non-javascript version of this page
. We're sorry about the hassle.
Actually, it is not possible to manage such a cache system in hardware, for a simple reason being that the total number of "sets" in the cache is not a power of two and via simple bits extraction mechanism it will be impossible to map some words addresses to correct sets in the cache and also be able to know where they are in the cache when the only thing used to match the correct cache word is tag matching.