A schematic

$G=\overline { \overline { w\cdot x\cdot y } } +\overline { \overline { y\cdot z } } =w\cdot x\cdot y+y\cdot z=y\left( w\cdot x+z \right)$

The output of two NAND gate are

(W * X * Y)' and (Y * Z)'.These are the two input of NOR gate and the output of NOR gate will be

[(W * X * Y)'+(Y * Z)']'

by de morgan's law:

A'+B'=(A * B)'

So,by using this formula we can easily get the answer which is Y(W * X+Z).

The output of two NAND gate are (WXY)' and (YZ)'.These are the two input of NOR gate and the output of NOR gate will be [(WXY)'+(YZ)']' by de morgan's law: A'+B'=(AB)' So,by using de morgan's can easily get the answer which is Y(WX+Z).

output of two NAND gate will be (WXY)' + (YZ)'. these will be the input for the NOR gate and G will be (WXY)+(YZ) and then simplied it to G = Y(WX+Z)

since 3 input nand gate is being used therefore your boolean algebra is (WXY)' then the 2 input NANd gate is being inputted by YZ then your boolean algebra => (YZ)' So active low input OR gate is being input by (WXY)' and (YZ)' then G = WXY + YZ further simplify G = Y( WX + Z)